A conventional delay cell 100 is shown in FIG. 1. The delay cell 100 includes a plurality of Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs), such as 104 and 106. MOSFETs 104 and 106 comprise a differential pair, which switches the current 110 from one output leg to another output leg based on the voltage difference between input voltages 112 and 114. When the difference between input voltages 112 and 114 is greater than zero, current 110 flows in output leg 120. If the difference between the input voltages is less than zero, current flows in output leg 122.
The delay cell 100 includes a current source 108, voltage-controlled resistances 124 and 126, and output load capacitances 130 and 132. The voltage-controlled resistances 124 and 126 control the delay of the circuit 100. The delay is defined by the time it takes the RC (voltage controlled resistance-load capacitance product) voltage rise of one output leg of the delay cell to equal the RC voltage decay of the other output leg after the difference of inputs 114 and 118 transitions, switching the current 110 from one output leg to the other output leg. This is modeled by the following equation: IR(1−e−1/RC)=I RE−1/RC, where I is the current 110 provided by the current source 108 and t is the time delay. Solving for t, the delay through delay cell 100 is t=RCln(2). At low output voltage, the voltage controlled resistances 124 and 126 are modeled by the following equation: R=1/Gm=1/B(VC−VTHN), where Gm is an NMOS transconductance, VC is the control voltage 102, VTHN is the NMOS threshold voltage, and B is the product of the W/L ratio (width divided by length of the transistor), the oxide capacitance COX, and the MOSFET channel mobility. In a ring oscillator composed of N delay cells, the frequency of the circuit is approximately   F  =            1              2        ⁢                                   ⁢        N        ×        t              =                            B          ⁡                      (                                          V                C                            -                              V                THN                                      )                                    2          ⁢                                           ⁢          NC          ⁢                                           ⁢                      ln            ⁡                          (              2              )                                          .      
Further discussion of conventional delay cells can be found in the articles “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” by John Maneatis, IEEE Journal of Solid-State Circuits: Vol. 31, No. 11, November 1996, pp. 1723-1732; and “A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability” by Patrik Larsson, IEEE Journal of Solid-State Circuits: Vol. 34, No. 12, December 1999, pp. 1951-1960.
Since the output voltage of the delay cell 100 is between 0 and IR, and R can vary by as much as 5 times to modulate the delay, the value of I must track R to maintain sufficient output voltage swing (VOUT-MAX=IR) in the circuit to sustain the signal through a series of delay cells, such as in a delay line or ring oscillator. A feedback structure must -be used to set the product IR equal to a constant reference voltage (VOUT-MAX=VREF). This makes the delay of the conventional delay cell 100 sensitive to changes in I. Since I=VREF/R is set by a compensated feedback loop, changes to I occur much more slowly than changes in R for varying control voltage VC. Rapid changes in VC and R can cause short-term amplitude modulation in VOUT-MAX, which will cause delay modulation. VOUT-MAX can also drop low enough within the delay cell to prevent the triggering of the next delay cell in the series, disabling the voltage controlled oscillator (VCO) or delay line of which it is a part of. A solution to this problem is to limit the voltage control signal (VC) modulation bandwidth of the VCO or delay line utilizing this cell. For a phase lock loop (PLL) or delay locked loop (DLL), limiting the modulation bandwidth of the loop's VCO or delay line directly limits the bandwidth of the system.
The conventional delay cell also has a limited linear voltage control range. Beyond a certain range of VC, the voltage-controlled resistances 124 and 126 are no longer a linear function of VC. PLL stability design is more difficult using VCOs with non-linear frequency control and can generate PLLs with greater output noise.